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Robust Design for Emerging Nanotechnologies such as Carbon Nanotubes

Students

Nishant Patil
Hai Wei
Jerry Zhang

Overview

One-dimensional nanodevices such as Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silicon CMOS. An ideal CNFET technology may enable digital systems with 13X Energy-Delay-Product advantage compared to Si-CMOS with the same lithographic groundrules. However, a major gap exists between such ideal scenarios and practical designs using CNFETs. Fundamental limitations include misaligned carbon nanotubes (CNTs), metallic CNTs, and device integration with high density. We adopt an interdisciplinary approach (jointly with Prof. H.-S. Philip Wong and Prof. Hongjie Dai of Stanford, and Prof. Chongwu Zhou of USC) to overcome these limitations and experimentally demonstrate working CNFET circuits. Recently, we developed a technique for designing CNFET logic circuits that are guaranteed to implement correct logic functions even in the presence of a large number of misaligned CNTs. We are currently developing an approach for designing metallic-CNT-immune circuits by combining new design techniques with CNFET modeling and processing techniques. The ultimate question that motivates our research is: given the opportunities with CNFET devices – fine pitch, excellent device characteristics – what can be gained at the circuit-level compared to cutting-edge silicon CMOS?

Selected Publications

J. Zhang, N. Patil, A. Hazeghi and S. Mitra, "Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations," IEEE/ACM Design Automation Conference, San Francisco, CA, July 2009.
- Supplemental Technical Report (pdf)
A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong, "A Metallic-CNT-Tolerant Carbon Nanotube Technology using Asymmetrically-Correlated CNTs (ACCNT)," VLSI Technology Symp., Kyoto, Japan, June 2009.
S. Mitra, J. Zhang, N. Patil and H. Wei, “Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube FETs,” IEEE/ACM Design Automation and Test in Europe (DATE), 2009 (Invited).
J. Zhang, N. Patil and S. Mitra, “Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,” IEEE Trans. CAD , 2009.
N. Patil, A. Lin, E. Myers, K. Ryu, A. Badmaev, C. Zhou, H.-S.P. Wong and S. Mitra, “Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes,” IEEE Trans. Nanotechnology, 2009.
N. Patil, J. Deng, H.S.-P. Wong and S. Mitra, “Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits,” IEEE Trans. Nanotechnology, 2009.
K. Ryu, A. Badmaev, C. Wang, A. Lin, N. Patil, L. Gomez, A. Kumar, S. Mitra, H.-S.P. Wong and C. Zhou, “CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes,” Nanoletters, Vol. 9, Issue 1, pp 189–197, Jan. 2009.
A. Lin, N. Patil, A. Badmaev, L. Gomez De Arco, C. Zhou, S. Mitra and H.S.-P. Wong, “Threshold Voltage and On-Off Ratio Tuning for Multiple-tube Carbon Nanotube FETs,” IEEE Trans. Nanotechnology, 2009.
N. Patil, J. Deng, A. Lin, H.S.-P. Wong and S. Mitra, "Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits," IEEE Trans. Computer-Aided Design, Oct 2008.
N. Patil, J. Deng, H.S.-P. Wong and S. Mitra, "Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits," IEEE Trans. Nanotechnology, 2008.
A. Lin, N. Patil, A. Badmaev, L. Gomez De Arco, C. Zhou, S. Mitra and H.S.-P. Wong, "Threshold Voltage and On-Off Ratio Tuning for Multiple-tube Carbon Nanotube FETs," IEEE Trans. Nanotechnology.
N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, "Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures," 2008 Symp. VLSI Technology, 2008.
J. Zhang, N. Patil and S. Mitra, "Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits," Design Automation and Test in Europe, 2008
N. Patil, J. Deng, H.-S.P. Wong and S. Mitra, “Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits,” Design Automation Conference, 2007
J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra and H.-S.P. Wong, “Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections,” Intl. Solid State Circuits Conf. (ISSCC), 2007
N. Patil, J. Deng, S. Mitra and H.-S.P. Wong, “Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits,” GomacTech, 2007 (Invited).
J. Deng, N.P. Patil, S. Mitra and H.S.P. Wong, “Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions,” IEEE Nano, 2006 (Invited).