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Robust Design for Emerging Nanotechnologies such as Carbon Nanotubes

Students

  • Hai Wei
  • Max Shulaker
  • Gage Hill

Overview

One-dimensional nanodevices such as Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silicon CMOS. An ideal CNFET technology may enable digital systems with 13X Energy-Delay-Product advantage compared to Si-CMOS with the same lithographic groundrules. However, a major gap exists between such ideal scenarios and practical designs using CNFETs. Fundamental limitations include misaligned carbon nanotubes (CNTs), metallic CNTs, and device integration with high density. We adopt an interdisciplinary approach (jointly with Prof. H.-S. Philip Wong and Prof. Hongjie Dai of Stanford, and Prof. Chongwu Zhou of USC) to overcome these limitations and experimentally demonstrate working CNFET circuits. Recently, we developed a technique for designing CNFET logic circuits that are guaranteed to implement correct logic functions even in the presence of a large number of misaligned CNTs. We are currently developing an approach for designing metallic-CNT-immune circuits by combining new design techniques with CNFET modeling and processing techniques. The ultimate question that motivates our research is: given the opportunities with CNFET devices – fine pitch, excellent device characteristics – what can be gained at the circuit-level compared to cutting-edge silicon CMOS?

Selected Publications

* Journal Publications:*

M. Shulaker, H. Wei, N. Patil, J. Provine, H. Chen, H.-S.P. Wong and S. Mitra, “Linear Increases in Carbon Nanotube Density Through Multiple Transfer Technique,” Nanoletters, 2011.

J. Zhang, N. Patil, A. Hazeghi, H.-S.P. Wong and S. Mitra, “Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations,” IEEE Trans. CAD, 2011.

N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong and S. Mitra, “Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mis-positioned Carbon Nanotubes,” IEEE Trans. Nanotechnology, 2010.

A. Lin, N. Patil, J. Zhang, H. Wei, S. Mitra and H.-S.P. Wong, “ACCNT - A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines,” IEEE Trans. Electron Devices, 2010.

A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong, “ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Concepts and Experimental Demonstration,” IEEE Trans. Electron Devices , 2009.

J. Zhang, N. Patil and S. Mitra, “Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,” IEEE Trans. CAD , 2009.

N. Patil, A. Lin, E. Myers, K. Ryu, A. Badmaev, C. Zhou, H.-S.P. Wong and S. Mitra, “Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes,” IEEE Trans. Nanotechnology, 2009.

N. Patil, J. Deng, H.S.-P. Wong and S. Mitra, “Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits,” IEEE Trans. Nanotechnology, 2009.

A. Lin, N. Patil, A. Badmaev, L. Gomez De Arco, C. Zhou, S. Mitra and H.S.-P. Wong, “Threshold Voltage and On-Off Ratio Tuning for Multiple-tube Carbon Nanotube FETs,” IEEE Trans. Nanotechnology, 2009.

N. Patil, J. Deng, A. Lin, H.S.-P. Wong and S. Mitra, “Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits,” IEEE Trans. Computer-Aided Design, 2008.

C. Wang, K. Ryu, A. Badmaev, N. Patil, A. Lin, S. Mitra, H.-S. P. Wong and C. Zhou, “Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes,” Applied Physics Letters, 93, 033101 , 2008.

Conference Publications:

J. Zhang, N. Patil, H.-S.P. Wong and S. Mitra, “Overcoming Carbon Nanotube Variations through Co-optimized Technology and Circuit Design,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.

H.-S.P. Wong, S. Mitra, D. Akinwande, C. Beasley, Y. Chai, H. Chen, X. Chen, G. Close, J. Deng, A. Hazeghi, J. Liang, A. Lin, L. Liyanage, J. Luo, J. Parker, N. Patil, M. Shulaker, H. Wei, L. Wei, J. Zhang, “Carbon Nanotube Electronics – Materials, Devices, Circuits, Design, Modeling, and Performance Projection,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011 (Invited).

S. Chong, B. Lee, K. Parizi, J. Provine, S. Mitra, R. Howe and H.-S.P. Wong, “Integration of Nanoelectromechanical (NEM) Relays with Silicon CMOS with Functional CMOS-NEM Circuit,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.

H. Wei, H. Chen, L. Liyanage, H.-S.P. Wong and S. Mitra, “Air-Stable Technique for Fabricating n-Type Carbon Nanotube FETs,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.

H. Chen, N. Patil, A. Lin, L. Wei, C. Beasley, J. Zhang, X. Chen, H. Wei, L.S. Liyanage, M. Shulaker, S. Mitra and H.-S.P. Wong, “Carbon Electronics – From Material Synthesis to Circuit Demonstration,” Intl. Symp. VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, 2011 (Invited).

J. Zhang, S. Bobba, N. Patil, A. Lin, H.-S.P. Wong, G. De Micheli and S. Mitra, “Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement,” IEEE/ACM Design Automation Conference, Anaheim, CA, June 2010.

H. Wei, N. Patil, J. Zhang, A. Lin, H. Chen, H.-S.P. Wong and S. Mitra, “Efficient Metallic Carbon Nanotube Removal Readily Scalable to Wafer-Level VLSI CNFET Circuits,” Symposium VLSI Technology, Honolulu, Hawaii, June 2010.

J. Zhang, N. Patil, A. Lin, H.-S.P. Wong and S. Mitra, “Carbon Nanotube Circuits: Living with Imperfections and Variations,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010 (Invited).

N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong and S. Mitra, “VMR: VLSI-Compatible Metallic Carbon Nanotube Removal for Imperfection-Immune Cascaded Multi-Stage Digital Logic Circuits using Carbon Nanotube FETs,” IEEE Intl. Electron Devices Meeting, Baltimore, MD, Dec. 2009.

H. Wei, N. Patil, A. Lin, H.-S.P. Wong and S. Mitra, “Monolithic Three-Dimensional Integrated Circuits using Carbon Nanotube FETs and Interconnects,” IEEE Intl. Electron Devices Meeting, Baltimore, MD, Dec. 2009.

N. Patil, A. Lin, J. Zhang, H.-S.P. Wong and S. Mitra, “Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions,” IEEE/ACM Design Automation Conference, San Francisco, CA, July 2009 (Invited).

J. Zhang, N. Patil, A. Hazeghi and S. Mitra, “Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations,” IEEE/ACM Design Automation Conference, San Francisco, CA, July 2009.

A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong, “A Metallic-CNT-Tolerant Carbon Nanotube Technology using Asymmetrically-Correlated CNTs (ACCNT),” VLSI Technology Symp., Kyoto, Japan, June 2009.

S. Mitra, J. Zhang, N. Patil and H. Wei, “Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube FETs,” IEEE/ACM Design Automation and Test in Europe (DATE), Nice, France, April 2009 (Invited).

N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, “Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures,” 2008 Symp. VLSI Technology, Honolulu, Hawaii, June 2008.

S. Mitra, N. Patil and J. Zhang, “Imperfection-Immune Carbon Nanotube VLSI Logic Circuits,” Foundations of NANO (FNANO), Snowbird, UT, April 2008 (Invited).

J. Zhang, N. Patil and S. Mitra, “Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits,” Design Automation and Test in Europe, Munich, Germany, March 2008.

N. Patil, J. Deng, H.-S.P. Wong and S. Mitra, “Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits,” Design Automation Conference, San Diego, CA, June 2007.

J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra and H.-S.P. Wong, “Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections,” Intl. Solid State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 2007.

N. Patil, J. Deng, S. Mitra and H.-S.P. Wong, “Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits,” GomacTech? , Orlando, FL, March 2007 (Invited).

J. Deng, N.P. Patil, S. Mitra and H.S.P. Wong, “Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions,” IEEE Nano, 2006 (Invited).

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