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Research Thrust: Effective Post-Silicon Validation

Robust system design must address not only reliability failures but also design errors that may be caused by incorrect modeling, incorrect understanding of specifications or human mistakes. Our idea is to create new, low-cost design structures and system-level analysis techniques that enable effective system-level fault isolation and allow us to formally reason about incorrect behaviors in a system setup. [ LINK ]

Research Thrust: Overcoming CMOS Reliability Challenges

The traditional design paradigm that assumes that no gate or interconnect will ever operate incorrectly during the lifetime of a design (except for high-end mainframes and safety-critical applications). will become infeasible in future technologies. Our central vision is to develop enabling technologies and tools spanning multiple abstraction levels to design globally optimized robust systems targeting a wide range of applications without incurring the high cost of classical redundancy. [ LINK ]

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Research Thrust: Emerging Nanotechnologies such as Carbon Nantobues and Nano-Electro-Mechanical Switches

One-dimensional nanodevices such as Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silicon CMOS. An ideal CNFET technology may enable digital systems with 13X Energy-Delay-Product advantage compared to Si-CMOS with the same lithographic groundrules. However, a major gap exists between such ideal scenarios and practical designs using CNFETs. We adopt an interdisciplinary approach (jointly with Prof. H.-S. Philip Wong and Prof. Hongjie Dai of Stanford, and Prof. Chongwu Zhou of USC) to overcome these limitations and experimentally demonstrate working CNFET circuits. [ LINK ]

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