Selected Publications

This list consists of a selected set of publications on recent research results. A complete list of publications is available here.

Efficient Techniques to Overcome Scaled-CMOS Reliability Challenges

• T.W. Chen, Y.M. Kim, K. Kim, Y. Kameda, M. Mizuno and S. Mitra, “Experimental Study of Gate-Oxide Early Life Failures,” Intl. Reliability Physics Symp., 2009.
• H. Inoue, Y. Li and S. Mitra, “VAST: Virtualization Assisted Concurrent Autonomous Self-Test,” Intl. Test Conf., 2008.
• M. Agarwal, et al., “Optimized Circuit Failure Prediction for Aging: Practicality and Promise,” Intl. Test Conf., 2008.
• I. Loi, et al., "A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network-on-Chip Links," Intl. Conf. CAD (ICCAD), 2008.
• T.W. Chen, K. Kim, Y. Kim and S. Mitra, “Gate-Oxide Early Life Failure Prediction,” IEEE VLSI Test Symp., 2008.
• Y. Li, S. Makar and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns," Design Automation and Test in Europe, 2008
• S. Mitra, "Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges," Design Automation and Test in Europe, 2008 (Invited)
• S. Mitra, "Circuit Failure Prediction for Robust System Design in Scaled CMOS," International Reliability Physics Symp., 2008 (Invited)
• M. Agarwal, B. Paul, M. Zhang and S. Mitra, “Circuit Failure Prediction and Its Application to Transistor Aging,” IEEE VLSI Test Symp., 2007
• S. Mitra and M. Agarwal, “Circuit Failure Prediction to Overcome Scaled CMOS Reliability Challenges,” Intl. Test Conf., 2007 (Invited).
• P. Relangi and S. Mitra, “Erratic Bit Errors in Latches,” Intl. Reliability Physics Symp. (IRPS), 2007
• S. Seshia, W. Li and S. Mitra, “Verification Guided Soft Error Resilience,” Design Automation and Test in Europe, 2007
• S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas and K.S. Kim, “Combinational Logic Soft Error Correction,” Intl. Test Conf., 2006
• M. Zhang, S. Mitra, TM Mak, N. Seifert, Q. Shi, K.S. Kim, N. Shanbhag, N. Wang and S.J. Patel, “Sequential Element Design with Built-In Soft Error Resilience,” IEEE Trans. VLSI, 2006
• S. Mitra, M. Zhang, N. Seifert, T.M. Mak and K.S. Kim, “Soft Error Resilient System Design through Error Correction,” IFIP SOC-VLSI, 2006.
• S. Mitra, M. Zhang, T.M. Mak, N. Seifert, V. Zia and K.S. Kim, “Logic Soft Errors: A Major Barrier to Robust Platform Design,” Intl. Test Conf., 2005
• S. Mitra, T. Karnik, N. Seifert and M. Zhang, "Logic Soft Errors in Sub-65nm Technologies: Design and CAD Challenges," Design Automation Conf., 2005
• S. Mitra, N. Seifert, M. Zhang, Q. Shi and K.S. Kim, “Robust System Design with Built-In Soft Error Resilience,” IEEE Computer, Vol. 38, Number 2, pp. 43-52, Feb. 2005

Effective Validation of Robust Systems

• S. Park, T. Hong, and S. Mitra, "Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)," IEEE Trans. CAD, Oct 2009.
• S. Park and S. Mitra, "IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors," IEEE/ACM Design Automation Conf., 2008.
  • Supplemental Technical Report (pdf)

Robust Design for Emerging Nanotechnologies

• J. Zhang, N. Patil, A. Hazeghi and S. Mitra, "Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations," IEEE/ACM Design Automation Conference, San Francisco, CA, July 2009.
  • Supplemental Technical Report (pdf)
• A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong, "A Metallic-CNT-Tolerant Carbon Nanotube Technology using Asymmetrically-Correlated CNTs (ACCNT)," VLSI Technology Symp., Kyoto, Japan, June 2009.
• S. Mitra, J. Zhang, N. Patil and H. Wei, “Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube FETs,” IEEE/ACM Design Automation and Test in Europe (DATE), 2009 (Invited).
• J. Zhang, N. Patil and S. Mitra, “Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,” IEEE Trans. CAD , 2009.
• N. Patil, A. Lin, E. Myers, K. Ryu, A. Badmaev, C. Zhou, H.-S.P. Wong and S. Mitra, “Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes,” IEEE Trans. Nanotechnology, 2009.
• N. Patil, J. Deng, H.S.-P. Wong and S. Mitra, “Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits,” IEEE Trans. Nanotechnology, 2009.
• K. Ryu, A. Badmaev, C. Wang, A. Lin, N. Patil, L. Gomez, A. Kumar, S. Mitra, H.-S.P. Wong and C. Zhou, “CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes,” Nanoletters, Vol. 9, Issue 1, pp 189–197, Jan. 2009.
• A. Lin, N. Patil, A. Badmaev, L. Gomez De Arco, C. Zhou, S. Mitra and H.S.-P. Wong, “Threshold Voltage and On-Off Ratio Tuning for Multiple-tube Carbon Nanotube FETs,” IEEE Trans. Nanotechnology, 2009.
• N. Patil, J. Deng, A. Lin, H.S.-P. Wong and S. Mitra, "Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits," IEEE Trans. Computer-Aided Design, Oct 2008.
• N. Patil, J. Deng, H.S.-P. Wong and S. Mitra, "Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits," IEEE Trans. Nanotechnology, 2008.
• A. Lin, N. Patil, A. Badmaev, L. Gomez De Arco, C. Zhou, S. Mitra and H.S.-P. Wong, "Threshold Voltage and On-Off Ratio Tuning for Multiple-tube Carbon Nanotube FETs," IEEE Trans. Nanotechnology.
• N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, "Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures," 2008 Symp. VLSI Technology, 2008.
• J. Zhang, N. Patil and S. Mitra, "Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits," Design Automation and Test in Europe, 2008
• N. Patil, J. Deng, H.-S.P. Wong and S. Mitra, “Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits,” Design Automation Conference, 2007
• J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra and H.-S.P. Wong, “Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections,” Intl. Solid State Circuits Conf. (ISSCC), 2007
• N. Patil, J. Deng, S. Mitra and H.-S.P. Wong, “Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits,” GomacTech, 2007 (Invited).
• J. Deng, N.P. Patil, S. Mitra and H.S.P. Wong, “Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions,” IEEE Nano, 2006 (Invited).