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Selected Publications

This list consists of a selected (non-recent) set of publications on recent research results. A complete list of updated publications is available here.

Efficient Techniques to Overcome Scaled-CMOS Reliability Challenges

Journal publications:

E. Mintarno, J. Skaf, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R.W. Dutton and S. Mitra, “Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging,” IEEE Trans. CAD, 2011.

Y. Li, Y.M. Kim, E. Mintarno, D. Gardner and S. Mitra, “Overcoming Early-Life Failure and Aging Challenges for Robust System Design,” IEEE Design and Test of Computers, Special Issue on Design for Reliability and Robustness, 2009 (Invited).

T. Chen, C. Ito, W. Loh, W. Wang, K. Doddapaneni, S. Mitra and R.W. Dutton, “Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies,” IEEE Trans. Electron Devices, 2009.

S. Mitra, N.R. Saxena, and E.J. McCluskey? , “Efficient Design Diversity Estimation for Combinational Circuits,” IEEE Trans. Comp., Vol. 53, Issue 11, pp. 1,483-1,492, Nov. 2004.

M. Tahoori and S. Mitra, “Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configurations,” IEEE Trans. Computer-Aided Design, Vol. 23, Issue 2, pp. 261-272, Feb. 2004.

K.S. Kim, S. Mitra and P.G. Ryan, “Delay Defect Characteristics and Testing Strategies,” IEEE Design and Test of Computers, Special Issue on Speed Test and Speed Binning of Complex ICs, Vol. 20, Issue 5, pp. 8-16, Sept.-Oct. 2003.

S. Mitra, L.J. Avra and E.J. McCluskey? , “Efficient Multiplexer Synthesis,” IEEE Design and Test of Computers, Vol. 17, No. 4, pp. 90-97, Oct. – Dec. 2000.

Conference publications:

Y. Kim, Y. Kameda, H. Kim, M. Mizuno and S. Mitra, “Low-Cost Gate-Oxide Early-life Failure Detection in Robust Systems,” Symposium VLSI Circuits, Honolulu, Hawaii, June 2010.

Y. Kim, T. Chen, Y. Kameda, M. Mizuno and S. Mitra, “Gate-Oxide Early-life Failure Identification using Delay Shifts,” IEEE VLSI Test Symposium, Santa Cruz, CA, April 2010.

S. Mitra, K. Brelsford and P. Sanda, “Cross-Layer Resilience Challenges: Metrics and Optimization,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010 (Invited).

Y. Kanoria, A. Montanari and S. Mitra, “Statistical Static Timing Analysis using Markov Chain Monte Carlo,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010.

E. Mintarno, Y. Cao, S. Boyd, R. Dutton and S. Mitra, “Optimized Self-Tuning to Maximize Lifetime Energy-Efficiency in the Presence of Circuit Aging,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010.

R. Zheng, et al., “Circuit Aging Prediction for Low-Power Operation,” Custom Integrated Circuits Conf., San Jose, CA, Sept. 2009.

H. Baba and S. Mitra, “Testing for Transistor Aging,” IEEE VLSI Test Symp., Santa Cruz, CA, April 2009.

T.W. Chen, Y.M. Kim, K. Kim, Y. Kameda, M. Mizuno and S. Mitra, “Experimental Study of Gate-Oxide Early Life Failures,” Intl. Reliability Physics Symp., Toronto, Canada, April 2009.

M. Agarwal, et al., “Optimized Circuit Failure Prediction for Aging: Practicality and Promise,” Intl. Test Conf., Santa Clara, CA, Oct. 2008.

I. Loi, et al., “A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network-on-Chip Links,” Intl. Conf. CAD (ICCAD), San Jose, CA, Nov. 2008.

T.W. Chen, K. Kim, Y. Kim and S. Mitra, “Gate-Oxide Early Life Failure Prediction,” IEEE VLSI Test Symp., San Diego, CA, April 2008.

S. Mitra, “ Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges,” Design Automation and Test in Europe, Munich, Germany, March 2008 (Invited).

S. Mitra, “Circuit Failure Prediction for Robust System Design in Scaled CMOS,” International Reliability Physics Symp., Phoenix, AZ, May 2008 (Invited).

S. Mitra and M. Agarwal, “Circuit Failure Prediction to Overcome Scaled CMOS Reliability Challenges,” Intl. Test Conf., Santa Clara, CA, Oct. 2007 (Invited).

M. Agarwal, B. Paul and S. Mitra, “Circuit Failure Prediction and Its Application to Transistor Aging,” IEEE VLSI Test Symp., Berkeley, CA, April 2007.

P. Relangi and S. Mitra, “Erratic Bit Errors in Latches,” Intl. Reliability Physics Symp. (IRPS), Phoenix, AZ, April 2007.

S. Seshia, W. Li and S. Mitra, “Verification Guided Soft Error Resilience,” Design Automation and Test in Europe (DATE), Nice, France, April 2007.

T.W. Chen, C. Ito, W. Loh, W. Wang, S. Mitra and R.W. Dutton, “Marco-model for Post-breakdown 90nm and 130nm Transistors and its Applications in Predicting Chip-level Function Failure after ESD-CDM Events,” Intl. Reliability Physics Symp., Phoenix, AZ, April 2007.

N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra and J. Maiz, “Radiation Induced Soft Error Rates of Advanced CMOS Bulk Devices,” IEEE Intl. Reliability Physics Symp., 2006.

R. Guo, S. Mitra, J. Lee, S. Sivaraj and M. Ameen, "Comparison of Test Metrics: Stuck-at, N-Detect and Gate-Exhaustive," IEEE VLSI Test Symp., 2006.

D.J. Leavins, K.S. Kim, S. Mitra and E. Rodriguez, “Robust Platform Design in Sub-65nm Technologies,” Custom Integrated Circuits Conference, 2005, (Invited).

K.Y. Cho, S. Mitra and E.J. McCluskey? , “Gate Exhaustive Testing,” Intl. Test Conf., 2005.

S. Mitra, T. Karnik, N. Seifert and M. Zhang, “Logic Soft Errors in Sub-65nm Technologies: Design and CAD Challenges,” Design Automation Conf., 2005.

M. Tahoori, S. Mitra and E.J. McCluskey? , “Fault Grading FPGA Interconnect Test Configurations,” IEEE Intl. Test Conf., pp. 608-617, 2002.

Effective Validation of Robust Systems

Journal Publications:

S. Mitra, H. Cho, T. Hong, Y. Kim, H. Lee, L. Leem, Y. Li, D. Lin, E. Mintarno, S. Park, N. Patil, H. Wei and J. Zhang, “Robust System Design,” IPSJ Trans. System LSI Design Methodology, 2011 (Invited).

I. Loi, F. Angiolini, S. Mitra, S. Fujita and L. Benini, “Characterization and Implementation of Fault-Tolerant Vertical Links for 3D Networks-on-Chip,” IEEE Trans. CAD, 2010.

S. Park and S. Mitra, “Post-Silicon Bug Localization for Processors,” Research Highlight, Communications of the ACM, Feb. 2010 (Invited).

S. Park, T. Hong and S. Mitra, “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors,” IEEE Trans. CAD , 2009.

R. Kapur, S. Mitra, and T.W. Williams, “Historical Perspective of Scan Compression,” IEEE Design and Test of Computers, 2008 (Invited).

M. Zhang, S. Mitra, TM Mak, N. Seifert, Q. Shi, K.S. Kim, N. Shanbhag, N. Wang and S.J. Patel, “Sequential Element Design with Built-In Soft Error Resilience,” IEEE Trans. VLSI, Dec. 2006.

S. Mitra, N. Seifert, M. Zhang, Q. Shi and K.S. Kim, “Robust System Design with Built-In Soft Error Resilience,” IEEE Computer, Vol. 38, Number 2, pp. 43-52, Feb. 2005.

S. Mitra and K.S. Kim, “XPAND: An Efficient Test Stimulus Compression Technique,” IEEE Trans. Computers, Special Issue on System-on-Chip Design and Test, 2006.

S. Mitra, S. Lumetta, M. Mitzenmacher and N. Patil, “X-Tolerant Test Response Compaction,” IEEE Design and Test of Computers, Special Section on the 2005 International Test Conference, Nov.-Dec. 2005.

R.K. Iyer, N. Nakka, Z. Kalbarczyk and S. Mitra, “Recent Advances in Hardware-Level Reliability Support for Transient Errors,” IEEE MICRO, Special Issue on the Reliability-Aware Microarchitectures, Nov.-Dec. 2005.

A. Al-Yamani, S. Mitra and E.J. McCluskey? , “Optimized Reseeding by Seed Ordering and Encoding,” IEEE Trans. CAD, Feb. 2005.

S. Mitra, W. Huang. N.R. Saxena, S. Yu and E.J. McCluskey? , “Reconfigurable Architecture for Autonomous Self-Repair,” IEEE Design & Test of Computers, Special Issue on Yield & Reliability, Vol. 21, Issue 3, pp. 228-240, May-June 2004.

S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique,” IEEE Trans. Computer-Aided Design, Vol. 23, Issue 3, pp. 421-432, March 2004.

S. Mitra, N.R. Saxena and E.J. McCluskey? , “A Design Diversity Metric and Analysis of Redundant Systems,” IEEE Trans. Computers, Vol. 51, Issue 5, pp. 498-510, May 2002.

N.S. Oh, S. Mitra and E.J. McCluskey? , “ED4I: Error Detection by Diverse Data and Duplicated Instructions,” IEEE Trans. on Computers, Special Issue on Fault-Tolerant Embedded Systems, Vol. 51, Issue 2, pp. 180-199, Feb. 2002.

S. Mitra, N.R. Saxena and E.J. McCluskey? , “Common-Mode Failures in Redundant VLSI Systems: A Survey,” IEEE Trans. Reliability, Special Issue on Fault-Tolerant VLSI Systems, Vol. 49, Issue 3, pp. 285-295, Sept. 2000.

M.R. Saxena, S. Gomez, W. Huang, S. Mitra, S. Yu and E.J. McCluskey? , “Dependable Computing and On-Line Testing in Adaptive and Reconfigurable Systems,” IEEE Design and Test of Computers, Special Issue on Reconfigurable Computing, Vol. 17, No. 1, pp. 29-41, Jan. – Mar. 2000.

Conference Publications:

L. Leem, H. Cho, Y.M. Kim, H. Lee, Y. Li and S. Mitra, “Cross-Layer Error Resilience for Robust Systems,” IEEE/ACM Intl. Conf. Computer-Aided Design, San Jose, CA, Nov. 2010 (Invited).

T. Hong, Y. Li, S. Park, D. Mui, D. Lin, Z. Khaleq, N. Hakim, H. Naeimi, D. Gardner and S. Mitra, “QED: Quick Error Detection Tests for Effective Post-Silicon Validation,” IEEE International Test Conference, Austin, TX, Nov. 2010.

S. Park, A.C. Bracy, H. Wang and S. Mitra, “BLoG: Post-Silicon Bug Localization in Processors using Bug Localization Graphs,” IEEE/ACM Design Automation Conference, Anaheim, CA, June 2010.

S. Mitra, S. Seshia and N. Nicolici, “Post-Silicon Validation: Opportunities, Challenges and Recent Advances,” IEEE/ACM Design Automation Conference, Anaheim, CA, June 2010 (Invited).

H. Lee, K. Lilja, M. Bounasser, P. Relangi, I. Linscott, U. Inan and S. Mitra, “LEAP: Layout Design through Error-Aware Placement for Soft-Error Resilient Sequential Cell Design,” IEEE Intl. Reliability Physics Symposium, Anaheim, CA, May 2010.

Y. Li, D. Gardner and S. Mitra, “Concurrent Autonomous Self-Test for Uncore Components in SoCs? ,” IEEE VLSI Test Symposium, Santa Cruz, CA, April 2010.

L. Leem, H. Cho, J. Bau, Q. Jacobson and S. Mitra, “ERSA: Error-Resilient System Architecture for Probabilistic Applications,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010.

S. Mitra, “Robust System Design,” IEEE Intl. Conf. VLSI Design, Bangalore, India, Jan. 2010 (Invited).

Y. Li, O. Mutlu and S. Mitra, “Operating System Scheduling for Efficient On-line Self-Test in Robust Systems,” IEEE/ACM Intl. Conf. Computer-Aided Design, San Jose, CA, Nov. 2009.

H. Inoue, Y. Li and S. Mitra, “VAST: Virtualization Assisted Concurrent Autonomous Self-Test,” Intl. Test Conf., Santa Clara, CA, Oct. 2008.

S. Park and S. Mitra, “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors,” IEEE/ACM Design Automation Conf., Anaheim, CA, June 2008.

Y. Li, S. Makar and S. Mitra, “CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns,” Design Automation and Test in Europe, Munich, Germany, March 2008.

S. Mitra, M. Zhang, N. Seifert, TM Mak and K.S. Kim, “Built-In Soft Error Resilience for Robust System Design,” Intl. Conf. Integrated Circuit Design and Technology, Austin, TX, June 2007 (Invited).

K.Y. Cho, S. Mitra and E.J. McCluskey? , “California Scan: A Scan Architecture to Utilize Don't Care Bits in Test Patterns,” Intl. Test Conf., Santa Clara, CA, Oct. 2007.

B. Mungamuru, H. Garcia Molina, and S. Mitra, “How to Safeguard your Sensitive Data,” Intl. Symp. Reliable Distributed Systems, 2006.

S. Mitra, M. Zhang, N. Seifert, T.M. Mak, and K.S. Kim, “Soft Error Resilient System Design through Error Correction,” IFIP SOC VLSI, 2006 (Invited).

S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas and K.S. Kim, “Combinational Logic Soft Error Correction,” IEEE Intl. Test Conf., 2006.

N.P. Patil, S. Mitra and S.S. Lumetta, “Signature Analyzer Design for Yield Learning Support,” IEEE Intl. Test Conf., 2006.

M. Tahoori and S. Mitra, “Test Compression for FPGAs,” IEEE Intl. Test Conf., 2006.

S. Mitra, M. Zhang, T.M. Mak, N. Seifert, V. Zia and K.S. Kim, “Logic Soft Errors: A Major Barrier to Robust Platform Design,” Intl. Test Conf., 2005.

Z. Stanojevic. R. Guo, S. Mitra and S. Venkataraman, “Enabling Yield Analysis with X-Compact,” Intl. Test Conf., 2005.

T.M. Mak, S. Mitra and M. Zhang, “DFT Assisted Built-In Soft Error Resilience,” IEEE Intl. On-line Test Symp., 2005, (Invited).

S. Mitra, “Built-In Soft Error Resilience Techniques,” IEEE VLSI Test Symp., 2005, (Invited).

S. Mitra, K.S. Kim, T.M. Mak, N. Seifert, P. Shipley, M. Zhang and V. Zia, “Built-In Soft Error Resilience Structures,” Intel Design and Test Technology Conference, 2005.

Z. Stanojevic, R. Guo, S. Mitra and S. Venkataraman, “Fault Diagnosis with X-Compact,” Intel Design and Test Technology Conference, 2005.

E. Volkerink and S. Mitra, “Test Response Compression with Any Number of Unknowns,” Design Automation Conference, 2005.

S. Mitra, S. Lumetta and M. Mitzenmacher, “X-Tolerant Signature Analysis,” IEEE Intl. Test Conf., pp. 432-441, 2004.

K. Brand, S.Mitra, E. Volkerink and E.J. McCluskey? , “Speed Clustering of Integrated Circuits,” IEEE Intl. Test Conf., pp. 1128-1137, 2004.

M. Tahoori and S. Mitra, “Interconnect Delay Testing of Designs on Programmable Logic Devices,” IEEE Intl. Test Conf., 2004.

S. Mitra and K.S. Kim, “XPAND: Test Stimulus Compression for Intel Designs,” Intel Design and Test Technology Conf., 2004.

P. Johnson, D. Wu, S. Mitra and S. Venkataraman, “Elimination of System Test from Production Test Flow,” Intel Quality and Reliability Technical Symp., 2004.

S. Mitra and K.S. Kim, “Xpand + X-Compact: What did we Learn?”, IEEE VLSI Test Symp., 2004 (Invited).

S. Mitra, E. Volkerink, E.J. McCluskey? and S. Eichenberger, “Delay Defect Screening using Process Monitor Structures,” IEEE VLSI Test Symp., pp. 43-48, 2004.

E.J. McCluskey? , S. Mitra, et al., “ELF-MURPHY Data on Defects and Test Sets,” IEEE VLSI Test Symp., pp. 16-22, 2004.

M. Tahoori and S. Mitra, “Defect and Fault Tolerance for Reconfigurable Molecular Computing,” IEEE Field Programmable Custom Computing Machines (FCCM), pp. 176-185, 2004.

S. Mitra, H. Nguyen, N. Tam and K.S. Kim, “Soft Errors in Digital Logic,” Intel Quality and Reliability Technical Symp., 2003.

S. Mitra and K.S. Kim, “XMAX: X-Tolerant Architecture for Maximal Test Compression,” IEEE Intl. Conf. Computer Design, pp. 326-330, 2003. (Invited)

S. Lumetta and S. Mitra, “X-Codes: Error Control with Unknowable Inputs,” IEEE Intl. Symp. Information Theory, p. 102, 2003.

D. Wu, M. Lin, S. Mitra, et al., “H-DFT: A Hybrid DFT Architecture for Low-Cost High Quality Structural Testing,” IEEE Intl. Test Conf., pp. 1229-1238, 2003.

S. Mitra, S. Kallepalli and K.S. Kim, “Analysis of X-Compact for Intel ASIC Designs,” Intel Design and Test Technology Conf., 2003.

S. Mitra, K.S. Kim and G.C. Parrish, “Design for Guaranteed Test Stimulus Compression,” Intel Design and Test Technology Conf., 2003.

E. Volkerink and S. Mitra, “Efficient Seed Utilization for Reseeding based Compression,” IEEE VLSI Test Symp., pp. 232-237, 2003.

M. Tahoori and S. Mitra, “Automatic Configuration Generation for FPGA Interconnect Testing,” IEEE VLSI Test Symp., pp. 134-139, 2003.

A. Al Yamani, S. Mitra and E.J. McCluskey? , “BIST Reseeding with Very Few Seeds,” IEEE VLSI Test Symp. , pp. 69-74, 2003.

S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” IEEE Intl. Test Conf., pp. 311-320, 2002.

E. Volkerink, S. Mitra and A. Khoche, “Packet Based Test Vector Compression Techniques,” IEEE Intl. Test Conf., pp. 154-163, 2002.

S. Mitra and K.S. Kim, “Efficient Response Compaction,” Intel Design and Test Technology Conf., July 2002.

A. Khoche, S. Mitra and E. Volkerink, “Test Vector Compression using EDA-ATE Synergies,” IEEE VLSI Test Symp., pp. 97-102, 2002.

S. Mitra and E.J. McCluskey? , “Dependable Reconfigurable Computing: Design Diversity and Self-Repair,” NASA/DoD Intl. Conf. Evolvable Hardware, 2002. (Invited)

S. Mitra, E.J. McCluskey? and S. Makar, “Design for Testability and Testing of IEEE 1149.1 TAP Controller,” IEEE VLSI Test Symp., pp. 247-252, 2002.

A. Al-Yamani, S. Mitra, E.J. McCluskey? , “Testing Digital Circuits with Constraints,” IEEE Intl. Symp. Defect Fault Tolerance, 2002.

S. Mitra, N. Saxena and E.J. McCluskey? , “Techniques for Estimation of Design Diversity for Combinational Logic Circuits,” IEEE Intl. Conf. Dependable Systems and Networks, pp. 25-34, 2001.

S. Mitra and E.J. McCluskey? , “Design Diversity for Concurrent Error Detection in Sequential Logic Circuits,” IEEE VLSI Test Symp., pp. 178-183, 2001.

S. Mitra and E.J. McCluskey? , “Design of Redundant Systems Protected Against Common-Mode Failures,” IEEE VLSI Test Symp., pp. 190-195, 2001.

W-J. Huang, S. Mitra and E. J. McCluskey? , “Fast Run-Time Fault Location for Dependable FPGA Applications,” IEEE Intl. Symp. Defect and Fault Tolerance, pp. 206-214, 2001.

C.W. Tseng, S. Mitra, E.J. McCluskey? and S. Davidson, “An Evaluation of Pseudo-Random Testing for Detecting Real Defects,” IEEE VLSI Test Symp., pp. 404-409, 2001.

S. Mitra and E.J. McCluskey? , “Which Concurrent Error Detection Scheme to Choose?,” IEEE Intl. Test Conf., pp. 985-994, 2000.

S. Mitra and E.J. McCluskey? , “Combinational Logic Synthesis for Diversity in Duplex Systems,” IEEE Intl. Test Conf., pp. 179-188, 2000.

S. Mitra and E.J. McCluskey? , “WORD VOTER: A New Voter Design for Triple Modular Redundant Systems,” IEEE VLSI Test Symp., pp. 465-470, 2000.

S. Mitra, N. Saxena and E.J. McCluskey? , “Fault Escapes in Duplex Systems,” IEEE VLSI Test Symp., pp. 453-458, 2000.

P. Shirvani, S. Mitra, J. Ebergen, and M. Rocken, “DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits,” Intl. Symp. Asynchronous Circuits and Systems, pp. 73-82, 2000.

S. Mitra, N.R. Saxena, and E.J. McCluskey? , “A Design Diversity Metric and Reliability Analysis For Redundant Systems,” IEEE Intl. Test Conf., pp. 662-671, 1999.

P. Shirvani, S. Mitra, et al., “Fault-Tolerance Projects at Stanford CRC,” Military Applications Programmable Devices Conf., P23, 1999.

S. Mitra, L.J. Avra and E.J. McCluskey? , “An Output Encoding Problem and a Solution Technique,” IEEE/ACM Intl. Conf. Computer-Aided Design, pp. 304-307, 1997.

S. Mitra, L.J. Avra and E.J. McCluskey? , “Scan Synthesis for One-hot Signals,” IEEE Intl. Test Conf., pp. 714-722, 1997.

Robust Design for Emerging Nanotechnologies

* Journal Publications:*

M. Shulaker, H. Wei, N. Patil, J. Provine, H. Chen, H.-S.P. Wong and S. Mitra, “Linear Increases in Carbon Nanotube Density Through Multiple Transfer Technique,” Nanoletters, 2011.

J. Zhang, N. Patil, A. Hazeghi, H.-S.P. Wong and S. Mitra, “Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations,” IEEE Trans. CAD, 2011.

N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong and S. Mitra, “Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mis-positioned Carbon Nanotubes,” IEEE Trans. Nanotechnology, 2010.

A. Lin, N. Patil, J. Zhang, H. Wei, S. Mitra and H.-S.P. Wong, “ACCNT - A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines,” IEEE Trans. Electron Devices, 2010.

A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong, “ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Concepts and Experimental Demonstration,” IEEE Trans. Electron Devices , 2009.

J. Zhang, N. Patil and S. Mitra, “Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits,” IEEE Trans. CAD , 2009.

N. Patil, A. Lin, E. Myers, K. Ryu, A. Badmaev, C. Zhou, H.-S.P. Wong and S. Mitra, “Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes,” IEEE Trans. Nanotechnology, 2009.

N. Patil, J. Deng, H.S.-P. Wong and S. Mitra, “Performance Benchmarking and Scalability of Carbon Nanotube Transistor Circuits,” IEEE Trans. Nanotechnology, 2009.

A. Lin, N. Patil, A. Badmaev, L. Gomez De Arco, C. Zhou, S. Mitra and H.S.-P. Wong, “Threshold Voltage and On-Off Ratio Tuning for Multiple-tube Carbon Nanotube FETs,” IEEE Trans. Nanotechnology, 2009.

N. Patil, J. Deng, A. Lin, H.S.-P. Wong and S. Mitra, “Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits,” IEEE Trans. Computer-Aided Design, 2008.

C. Wang, K. Ryu, A. Badmaev, N. Patil, A. Lin, S. Mitra, H.-S. P. Wong and C. Zhou, “Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes,” Applied Physics Letters, 93, 033101 , 2008.

Conference Publications:

J. Zhang, N. Patil, H.-S.P. Wong and S. Mitra, “Overcoming Carbon Nanotube Variations through Co-optimized Technology and Circuit Design,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.

H.-S.P. Wong, S. Mitra, D. Akinwande, C. Beasley, Y. Chai, H. Chen, X. Chen, G. Close, J. Deng, A. Hazeghi, J. Liang, A. Lin, L. Liyanage, J. Luo, J. Parker, N. Patil, M. Shulaker, H. Wei, L. Wei, J. Zhang, “Carbon Nanotube Electronics – Materials, Devices, Circuits, Design, Modeling, and Performance Projection,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011 (Invited).

S. Chong, B. Lee, K. Parizi, J. Provine, S. Mitra, R. Howe and H.-S.P. Wong, “Integration of Nanoelectromechanical (NEM) Relays with Silicon CMOS with Functional CMOS-NEM Circuit,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.

H. Wei, H. Chen, L. Liyanage, H.-S.P. Wong and S. Mitra, “Air-Stable Technique for Fabricating n-Type Carbon Nanotube FETs,” IEEE Intl. Electron Devices Meeting, Washington D.C., Dec. 2011.

H. Chen, N. Patil, A. Lin, L. Wei, C. Beasley, J. Zhang, X. Chen, H. Wei, L.S. Liyanage, M. Shulaker, S. Mitra and H.-S.P. Wong, “Carbon Electronics – From Material Synthesis to Circuit Demonstration,” Intl. Symp. VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, 2011 (Invited).

J. Zhang, S. Bobba, N. Patil, A. Lin, H.-S.P. Wong, G. De Micheli and S. Mitra, “Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement,” IEEE/ACM Design Automation Conference, Anaheim, CA, June 2010.

H. Wei, N. Patil, J. Zhang, A. Lin, H. Chen, H.-S.P. Wong and S. Mitra, “Efficient Metallic Carbon Nanotube Removal Readily Scalable to Wafer-Level VLSI CNFET Circuits,” Symposium VLSI Technology, Honolulu, Hawaii, June 2010.

J. Zhang, N. Patil, A. Lin, H.-S.P. Wong and S. Mitra, “Carbon Nanotube Circuits: Living with Imperfections and Variations,” IEEE/ACM Design Automation and Test in Europe, Dresden, Germany, March 2010 (Invited).

N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong and S. Mitra, “VMR: VLSI-Compatible Metallic Carbon Nanotube Removal for Imperfection-Immune Cascaded Multi-Stage Digital Logic Circuits using Carbon Nanotube FETs,” IEEE Intl. Electron Devices Meeting, Baltimore, MD, Dec. 2009.

H. Wei, N. Patil, A. Lin, H.-S.P. Wong and S. Mitra, “Monolithic Three-Dimensional Integrated Circuits using Carbon Nanotube FETs and Interconnects,” IEEE Intl. Electron Devices Meeting, Baltimore, MD, Dec. 2009.

N. Patil, A. Lin, J. Zhang, H.-S.P. Wong and S. Mitra, “Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions,” IEEE/ACM Design Automation Conference, San Francisco, CA, July 2009 (Invited).

J. Zhang, N. Patil, A. Hazeghi and S. Mitra, “Carbon Nanotube Circuits in the Presence of Carbon Nanotube Density Variations,” IEEE/ACM Design Automation Conference, San Francisco, CA, July 2009.

A. Lin, N. Patil, H. Wei, S. Mitra and H.-S.P. Wong, “A Metallic-CNT-Tolerant Carbon Nanotube Technology using Asymmetrically-Correlated CNTs (ACCNT),” VLSI Technology Symp., Kyoto, Japan, June 2009.

S. Mitra, J. Zhang, N. Patil and H. Wei, “Imperfection-Immune VLSI Logic Circuits using Carbon Nanotube FETs,” IEEE/ACM Design Automation and Test in Europe (DATE), Nice, France, April 2009 (Invited).

N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, “Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures,” 2008 Symp. VLSI Technology, Honolulu, Hawaii, June 2008.

S. Mitra, N. Patil and J. Zhang, “Imperfection-Immune Carbon Nanotube VLSI Logic Circuits,” Foundations of NANO (FNANO), Snowbird, UT, April 2008 (Invited).

J. Zhang, N. Patil and S. Mitra, “Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits,” Design Automation and Test in Europe, Munich, Germany, March 2008.

N. Patil, J. Deng, H.-S.P. Wong and S. Mitra, “Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits,” Design Automation Conference, San Diego, CA, June 2007.

J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra and H.-S.P. Wong, “Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections,” Intl. Solid State Circuits Conf. (ISSCC), San Francisco, CA, Feb. 2007.

N. Patil, J. Deng, S. Mitra and H.-S.P. Wong, “Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits,” GomacTech? , Orlando, FL, March 2007 (Invited).

J. Deng, N.P. Patil, S. Mitra and H.S.P. Wong, “Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions,” IEEE Nano, 2006 (Invited).

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