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Robust Design for Emerging Nanotechnologies such as Carbon Nanotubes

Students

Nishant Patil
Jerry Zhang

Overview

One-dimensional nanodevices such as Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silicon CMOS. An ideal CNFET technology may enable digital systems with 13X Energy-Delay-Product advantage compared to Si-CMOS with the same lithographic groundrules. However, a major gap exists between such ideal scenarios and practical designs using CNFETs. Fundamental limitations include misaligned carbon nanotubes (CNTs), metallic CNTs, and device integration with high density. We adopt an interdisciplinary approach (jointly with Prof. H.-S. Philip Wong and Prof. Hongjie Dai of Stanford, and Prof. Chongwu Zhou of USC) to overcome these limitations and experimentally demonstrate working CNFET circuits. Recently, we developed a technique for designing CNFET logic circuits that are guaranteed to implement correct logic functions even in the presence of a large number of misaligned CNTs. We are currently developing an approach for designing metallic-CNT-immune circuits by combining new design techniques with CNFET modeling and processing techniques. The ultimate question that motivates our research is: given the opportunities with CNFET devices – fine pitch, excellent device characteristics – what can be gained at the circuit-level compared to cutting-edge silicon CMOS?

Selected Publications

N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, “Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures,” 2008 Symp. VLSI Technology, 2008.
J. Zhang, N. Patil and S. Mitra, "Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits," Design Automation and Test in Europe, 2008
N. Patil, J. Deng, H.-S.P. Wong and S. Mitra, “Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits,” Design Automation Conference, 2007
J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra and H.-S.P. Wong, “Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections,” Intl. Solid State Circuits Conf. (ISSCC), 2007
N. Patil, J. Deng, S. Mitra and H.-S.P. Wong, “Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits,” GomacTech, 2007 (Invited).
J. Deng, N.P. Patil, S. Mitra and H.S.P. Wong, “Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions,” IEEE Nano, 2006 (Invited).