People

Affiliated Faculty

Prof. Subhasish Mitra
Departments of Electrical Engineering and Computer Science, Stanford University
Email: subh at stanford dot edu
Phone: 650-724-1915
http://www.stanford.edu/~subh

Prof. Mitra leads the Robust Systems Group at Stanford and his research interests include robust system design, VLSI design, test and CAD, computer architecture and design for future nanotechnologies. Prior to joining Stanford, he was a Principal Engineer at Intel Corporation. Prof. Mitra has co-authored more than 90 technical papers and several patents, and has invented design and test techniques that have seen wide-spread proliferation in the chip design industry. His X-Compact technique for test compression is used by 40+ major Intel products including microprocessors, chipsets, and communications chips; and is supported by major CAD tools. His recent work on imperfection-immune carbon-nanotube circuit design, jointly with his students and collaborators, has been highlighted in the MIT Technology Review, EE Times, and several other publications. Prof. Mitra's major honors include the National Science Foundation CAREER Award, Terman Fellowship, IEEE Circuits and Systems Society Donald O. Pederson Award, several Best Paper Awards, a Divisional Recognition Award from Intel for a Breakthrough Soft Error Protection Technology, and the Intel Achievement Award, Intels highest corporate honor, for the development and deployment of a breakthrough test compression technology.

Administrative Staff

Uma Mulukutla
Email: uma at cs dot stanford dot edu
Office: Gates Building, Room 303
Phone: 650-725-3726

Affiliated Students

Graduate

• Mridul Agarwal (Currently at AMD) - Circuit failure prediction
• Anshuman Bhuyan
• Tze Wee Chen (PhD Student in Prof. Dutton's group) - Circuit failure prediction
• Tom A. Deane - Trusted integrated circuits
• Ted Hong - Online Self-Test
• Kyunglok Kim - Circuit failure prediction
• Yanjing Li - Online Self-Test
• Yasi Li - Application-aware robust systems
• Sung-Boem Park - Design and analysis techniques for effective post-silicon validation
• Nishant P. Patil - Imperfection-immune Carbon Nanotube circuits
• Prasanthi Relangi - Soft and erratic bit error resilience
• Jie (Jerry) Zhang - Imperfection-immune Carbon Nanotube circuits

Former Undergraduates (REUs)

• Robert M. Beatty Jr.
• Spencer Chu
• David Wanyoike Mwaura
• Aditya Singh

Visitors

Visiting Professors

• Prof. Janak H. Patel (University of Illinois at Urbana-Champaign)

Visiting Researchers

• Hiroaki Inoue, NEC
• Igor Loi, University of Bologna, Italy

Former

• Christian Cruz
• Jin Yang (Tsinghua University)