Selected Publications

This list consists of a selected set of publications on recent research results. A complete list of publications is available here.

Efficient Techniques to Overcome Scaled-CMOS Reliability Challenges

• T.W. Chen, K. Kim, Y. Kim and S. Mitra, “Gate-Oxide Early Life Failure Prediction,” IEEE VLSI Test Symp., 2008.
• Y. Li, S. Makar and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns," Design Automation and Test in Europe, 2008
• S. Mitra, "Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges," Design Automation and Test in Europe, 2008 (Invited)
• S. Mitra, "Circuit Failure Prediction for Robust System Design in Scaled CMOS," International Reliability Physics Symp., 2008 (Invited)
• M. Agarwal, B. Paul, M. Zhang and S. Mitra, “Circuit Failure Prediction and Its Application to Transistor Aging,” IEEE VLSI Test Symp., 2007
• S. Mitra and M. Agarwal, “Circuit Failure Prediction to Overcome Scaled CMOS Reliability Challenges,” Intl. Test Conf., 2007 (Invited).
• P. Relangi and S. Mitra, “Erratic Bit Errors in Latches,” Intl. Reliability Physics Symp. (IRPS), 2007
• S. Seshia, W. Li and S. Mitra, “Verification Guided Soft Error Resilience,” Design Automation and Test in Europe, 2007
• S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas and K.S. Kim, “Combinational Logic Soft Error Correction,” Intl. Test Conf., 2006
• M. Zhang, S. Mitra, TM Mak, N. Seifert, Q. Shi, K.S. Kim, N. Shanbhag, N. Wang and S.J. Patel, “Sequential Element Design with Built-In Soft Error Resilience,” IEEE Trans. VLSI, 2006
• S. Mitra, M. Zhang, N. Seifert, T.M. Mak and K.S. Kim, “Soft Error Resilient System Design through Error Correction,” IFIP SOC-VLSI, 2006.
• S. Mitra, M. Zhang, T.M. Mak, N. Seifert, V. Zia and K.S. Kim, “Logic Soft Errors: A Major Barrier to Robust Platform Design,” Intl. Test Conf., 2005
• S. Mitra, T. Karnik, N. Seifert and M. Zhang, "Logic Soft Errors in Sub-65nm Technologies: Design and CAD Challenges," Design Automation Conf., 2005
• S. Mitra, N. Seifert, M. Zhang, Q. Shi and K.S. Kim, “Robust System Design with Built-In Soft Error Resilience,” IEEE Computer, Vol. 38, Number 2, pp. 43-52, Feb. 2005

Effective Validation of Robust Systems

• S. Park and S. Mitra, “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors,” IEEE/ACM Design Automation Conf., 2008.
  • To request a soft copy of the supplemental technical report, email sbpark84 at stanford dot edu

Robust Design for Emerging Nanotechnologies

• N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, “Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures,” 2008 Symp. VLSI Technology, 2008.
• J. Zhang, N. Patil and S. Mitra, "Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits," Design Automation and Test in Europe, 2008
• N. Patil, J. Deng, H.-S.P. Wong and S. Mitra, “Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits,” Design Automation Conference, 2007
• J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra and H.-S.P. Wong, “Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections,” Intl. Solid State Circuits Conf. (ISSCC), 2007
• N. Patil, J. Deng, S. Mitra and H.-S.P. Wong, “Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits,” GomacTech, 2007 (Invited).
• J. Deng, N.P. Patil, S. Mitra and H.S.P. Wong, “Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions,” IEEE Nano, 2006 (Invited).