Effective Validation of Robust Systems

Students

• Thomas Deane - Trusted integrated circuits
• Sung-Boem Park - Post-Silicon validation

Overview

Robust system design must address not only reliability failures but also design errors that may be caused by incorrect modeling, incorrect understanding of specifications or human mistakes. Our current project focuses on post-Silicon validation which poses a significant challenge for robust system design. Major post-Silicon debug challenges involve “electrical bugs” that may appear due to subtle reasons such as process variations, environment-induced variations, imprecise modeling or unexpected interactions among various parts of a system. While significant progress has been made in circuit-level debug, a major gap exists between such capabilities and system-level debug where the objective is to quickly isolate and locate a problem to a few design blocks from anomalous system-level behaviors. Our idea in this project is to create new, low-cost design structures and system-level analysis techniques that enable effective system-level fault isolation and allow us to formally reason about incorrect behaviors in a system setup. Efficient circuit-level debug techniques can then root-cause bugs much more easily resulting in significant gains in productivity, cost, time-to-market and time-to-volume.

Selected Publications

• S. Park and S. Mitra, “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors,” IEEE/ACM Design Automation Conf., 2008.
  • To request a soft copy of the supplemental technical report, email sbpark84 at stanford dot edu